1. Field of the Invention
This invention relates to logic circuits and, more particularly, to methods and apparatus for reducing the power utilized in programmable logic array circuits.
2. History of the Prior Art
Programmable logic arrays (PLAS) are arrays of gates which allow a plurality of input values to be manipulated in accordance with various Boolean functions. In a basic form, such an array comprises a first series of input conductors each of which may carry a binary input value and a second series of input conductors each of which may carry the inverse of the binary input value carried by an associated one of the first series of input conductors. These first and second input conductors are selectively joined to a third series of conductors each of which is connected to a plurality of AND gates. In the basic form of programmable logic array, the output of each AND gate (called a product term) is available at the input to each of a plurality of OR gates. Since any one of the input conductors may be selectively joined to each of the third series of conductors, all of the input conductors are available to each of the AND gates in this form of gate array. By connecting various AND gate outputs (product terms) to various OR gates, a particular Boolean function which is the sum of the products terms produced by the AND gates may be furnished at the output of any OR gate. Thus, the Boolean output function provided at the output of each of the OR gates is programmable by selecting the connections to be made between the input conductors and the conductors of the third series.
Because programmable logic grays are designed with a plurality of AND gates providing input to a plurality of OR gates from which output signals indicating the result of a logic function are derived, it will be understood that a very large number of input signals is reduced to a much smaller number of output signals. As the number of input conductors increases and the circuit traces are placed closer to one another, the inherent capacitance experienced by the individual circuits increases. Since the gating circuitry responds to a system clock, a plurality of circuit nodes exhibiting high capacitance are constantly changing voltage levels. This is typically true of all of the AND gates which produce the product terms in programmable logic arrays even though the data to be evaluated changes infrequently. The constant change of voltage levels requires a great deal of power because such a large amount of circuitry is utilized to generate the product terms.
Furthermore, in circuits including programmable logic arrays which provide clocked output signals, unless the circuitry is very accurately timed, output signals will tend to be generated before they have stabilized. If output circuitry responds to these signals before these signals have stabilized, power is required to drive the output to a first level and then more power is required to reverse the level. This also uses more power than is necessary.
It is desirable to reduce the amount of power required in programmable logic arrays while maintaining the ability of those circuits to provide the same functions at the same speed.